When a semiconductor device such as a metal-oxide-semiconductor field-effect transistors (MOSFETs) is scaled down through various technology nodes, high k dielectric material and metal are adopted to form a gate stack. When forming such a device, the metal layer is tuned to have a proper work function for n-type MOSFETs and p-type MOSFETs to achieve the designed threshold voltage of the device. Currently, the metal layer in n-type MOSFETs and the metal layer in p-type MOSFETs are patterned using by an etching process procedure. However, a dry etch used for patterning could result in metal gate and high k dielectric film plasma damage. In addition, the dry etch could cause photoresist residue, which is difficult to remove. On other side, a wet etch used for patterning could cause lateral etch issue and degrade N/P patterning profile.